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MX93000
FEATURES
* * * * * * * * * * * * * Single +5V power supply Sigma-Delta A/D D/A with digital filters Support u/A Law and 16-bit linear format On-chip automatic level control On-chip differential line driver On-chip digital volume control Programmable transmit/receive gain control Support switch paths for DAM (Digital Answering Machine) applications Easy interface to general purpose DSPs Easy read/write of control register by microprocessors Programmable power-down Support power-low/battery-low detection 28-pin DIP/SOP package
PRODUCT OVERVIEW
The MX93000 Special Codec integrates key functions of the analog-front-end of Digital Answering Machine (DAM) into a single integrated circuit. The MX93000 is intended to provide a complete, low cost, and single chip solution for telephone applications requiring a single +5V power supply. The MX93000 Special Codec is especially powerful when applied to some DAM models which are intended to meet different countries' specifications in the same system hardware. User can achieve this goal by simply setting control firmware. This benifit will help DAM system makers to save developing time and R/D resources. The A/D D/A converters are implemented with 2ndorder sigma-Delta modulators. The on-chip digital filters, which are carried out with 16-bit and 2's complement format, are used to get the required frequency response of a PCM Codec. The Codec can support 8-bit u/A law and linear format. For the latter, it is 16-bit format with 14-bit resolution . Before the A/D digitizing the voice-band analog signal into digital format, the analog signal can be processed by a built-in Automatic Level Control (ALC) and programmable Gain Amplifier (PGA). The ALC circuit controls the input level of A/D converter to about 1.5 Volt, so as to get a better signal to noise ratio during a low-level input. The PGA circuit is used to control the gain of different sources : microphone, aux or line input. After the digital data is converted into analog signal by the D/A converter, a fully differential line driver is supported to drive the telephone line directly without the need of external amplifier. On the other hand, the analog signal can be monitored by passing the analog signal to the on-chip volume control circuit, which can drive an external driver like LM386. In addition, the MX93000 supports switches and control registers so that users can program the Special Codec to be under line operations and all other specific operations of DAM. To enhance an easy read/write of control registers by microprocessors, the control data is clocked by the 8 kHz sampling clock and synchronized by SDEN\, where SDEN\ is coming from the output port of microprocessor by detecting one of the rising edge of 8 kHz clock.
PIN CONFIGURATION
28PIN SOP/DIP
SDATA SDEN\ DX DR FS MCLK VDD GND PRST BAT\ VBAT PDN\ VPOW LIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
SPK VR VREF FILT ALCC ALCRC PGAC AUX MIC AG AGND AVDD LOUT2 LOUT1
MX93000
P/N: PM0306
1
REV. 3.0, JUL 15, 1996
MX93000
SPECIAL DIAGRAM CODEC BLOCK
2
MX93000
FUNCTIONAL DESCRIPTION
PCM CODEC : This block includes A/D & D/A converters and all of the digital filters. A/D & D/A converters: which are implemented with 2nd-order sigma-delta modulation. Output formats are A-Law/u-Law/16-bit linear, where u/A laws are of CCITT specifications and the 16-bit linear data can get 14-bit resolution and higher linearity than that of u/A law. Digital filters : For the purpose of A/D out-of-band noise filtering and D/A image attenuation, digital filters are implemented on the same chip. The digital input applied to D/A converter can not be a dc signal other than idle (bits all zero), as limit cycles in the digital modulator at a level of -70 dBm will present at the analog output. POWER MANAGEMENT : The MX93000 supports the automatic power-down control and power supply detection. This function will work well even under 3V power supply. Regarding the power_down procedure please refer to register 4 description for details. POWER_LOW/BATTERY_LOW detectors : active low 2 comparators and references are used to check whether POWER_LOW/BATTERY_LOW or not. The relationship between POWER_ON_RESET and POWER_LOW/BATTERY_LOW is as the following table: (I) POWER_LOW (PDN\) (I) BATTERY_LOW (BAT\) (0)POWER_ON_RESET (PRST) 0 0 0 0 1 1 1 0 1 1 1 1
LINE DRIVER : Not only support the programmable gain from 0 to 22.5 dB with 16 steps and 1.5 dB/step, but also fully differentially drive -5 dBm power over 300 ohms. If switches SWE , SWJ , and SWK are opened, then the line driver will be muted to -70dB automatically. In addition, when SWJ or SWK are turned on, there are loss at the line driver output due to single-ended to fully-differential transform.
LINE_IN BUFFER : Buffer stage with selection of echo cancellation path or not. For the echo cancellation path, 3-6 dB cancellation can get it.
PROGRAMABLE GAIN CONTROL (PGA) : It supports 0 to 22.5 dB gain with 16 steps and 1.5dB/step. The gain value is controlled separately by 3 registers, where different input signal paths will have a different gain value, and when the input path is changed, the respective register value will keep no change.
3
MX93000
AUTOMATIC LEVEL CONTROL (ALC) : The ALC can support 36 dB gain with the attack time and release time controlled by C6 and R3 * C6, respectively.
SPK ATTENUATOR : Speaker output signal can be attenuated either by internal register or external resister. For the former, the attenuation is from 0 to -45 dB with 16 steps and -3.0dB/step. For the later, 10K ohms variable resistor is suggested. If switches SWF and SWH are open, then attenuator will be muted to -70dB automatically.
SERIAL_CONTROL_INTERFACE : To read/write the internal registers. SDEN\ (serial data enable) is used to start receiving control signal. 8kHz frame sync.is used to transmit/receive the serial data (SDATA).
CODEC_SERIAL_PORT : 4-pin signal will complete the data trasmitting/receiving. MCLK is not only the data rate but also the chip master clock. Currently, it is fixed at 1.536 MHz and the frame synchronization clock, Fs, is 8 kHz. For simplicity, the A/D and D/A are synchronous so that MCLK and Fs are enough. Data transfer of DX/DR are MSB first in both 8-bit and 16-bit formats.
VOLTAGE REFERENCE : Two 2.25V voltage references are on-chip generated . VREF is for external and AG is for internal uses. Both two pins need the decoupling capacitors AGND at all times. VREF can be used to bias the microphone, the level shift circuits, or others.
SWITCHES : There are 2 registers which are used to control all of the switches so that user can direct many different signal paths, of which 3 of them are : a) Path of normal operation MIC input --> SWA --> PGA/ALC --> SWC --> SWD --> PCM Codec Ain LOUT1/LOUT2 <-- LINE DRIVER <-- SWE <-- PCM Codec Aout b) Path of room monitor MIC input --> SWA --> PGA/ALC --> SWC --> SWJ --> Line Driver LINE IN --> Line Buffer --> SWI --> PCM Codec Ain c) Path of line play LINE IN --> SWA --> PGA/ALC --> SWC --> SWD --> PCM Codec Ain LOUT1/LOUT2 <-- Line Driver <-- SWE <-- PCM Codec Aout SPK <-- Attenuator <-- SWF <-- PCM Codec Aout
4
MX93000
SPECIFICATIONS
ANALOG INPUT PARAMETER Input Voltage with max S/(N+THD) MIC/AUX/LINE/FILT Input Resistance* Input Capacitance* 15 15 MIN TYP MAX UNITS
3.4
Vpp Kohm pF
PROGRAMMABLE GAIN AMPLIFIER PARAMETER Gain Range Step Size MIN 0 1.3 1.5 TYP MAX 22.5 1.7 UNITS dB dB
AUTOMATIC LEVEL CONTROL PARAMETER REG.5 D1=0 MIN TYP MAX 36 REG.5 D1=1 UNITS MIN TYP MAX 30 dB
Dynamic Range* THD* < 75 mVpp < 1 Vpp < 100 mVpp <1 Vpp
40 30 40 25
dB dB dB dB
ANALOG OUTPUT PARAMETER Line Driver: Gain Range Step Size Full Swing Output (@600 ohm load) -- Fully differential(LOUT1-LOUT2) -- Single Ended (LOUT1) External Load -- Resistance* -- Capacitance* 0.0 1.2 22.5 1.8 dB dB MIN TYP MAX UNITS
1.5
6.0 3.0
Vpp Vpp
300 200
ohm pF
5
MX93000
SPK Attenuator : Gain Range Step Size Full Swing Output External Load -- Resistance* -- Capacitance* Mute Attenuation* FILT (I/O) Input Resistance* Output Resistance* External Load -- Capacitance * AUX (I/O) Input Capacitance* Input Resistance* Output Resistance* External Load -- Capacitance*
-45 -3.5
-3.0
0.0 -2.4 3.0
dB dB Vpp
10 100 -70
Kohm pF dB
10 10
Kohm Kohm
1000
pF
15 20 1
pF Kohm Kohm
100
pF
VOLTAGE REFERENCE PARAMETER VREF Output VREF Output Current* MIN 2.0 TYP 2.25 800 MAX 2.5 UNITS V uA
COMPARATOR DETECTOR PARAMETER Comparator Transfer point Hysteresis* MIN 1.10 TYP 1.25 MAX 1.40 0.15 UNITS V V
6
MX93000
A/D PATH CHARACTERISTICS (Note 1) PARAMETER Dynamic Range (-40 dB FS) THD+N (-6 dB FS) THD+N (u Law) Interchannel Isolation* Line/AUX/MIC Gain Variation (Note 3) Frequency Response 50-60 300-3k 3.2k-3.4k 4K > 4.6 K MIN TYP 72 -50 -36 MAX UNITS dB dB dB
70 5
dB %
-25 -1.0 -0.9 -15 -32
+1.0 +0.25
dB dB dB dB dB
D/A PATH CHARACTERISTICS (Note 2) PARAMETER Dynamic Range (-40 dB FS) THD+N (-6 dB FS) Gain Variation (Note 3) Total Out-of-Band Energy .6 Fs to 20 KHz Frequency Response < 300 300-3k 3.2k-3.4k 4K > 4.6k MIN TYP 72 -50 5 MAX UNITS dB dB %
-50
dB
-0.25 -0.25 -0.9 -15 -32
+0.25 +0.25 +0.25
dB dB dB dB dB
7
MX93000
NOISE PARAMETER Idle-channel Noise (Note 4) -- A/D Path -- D/A Path VDD Power Supply Rejection (Note 5) -- A/D Channel -- D/A Channel AVDD Power Supply Rejection (Note 5) -- A/D Channel -- D/A Channel Crosstalk* -- A/D to D/A (Note 6) -- D/A to A/D (Note 7) MIN TYP MAX UNITS
-70 -70
dB dB
40 40
dB dB
-50 -50
dB dB
-65 -65
dB dB
DIGITAL STATIC SPECIFICATIONS PARAMETER High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Output Capacitance* Input Capacitance* MIN 2.0 0 2.4 TYP MAX VDD 0.8 VDD 0.4 15 15 UNITS Volt Volt Volt Volt pF pF
POWER SUPPLY PARAMETER Power Supply - Digital & Analog Power Supply Current -- Operating -- Analog (Note 8) -- Digital Power Supply Current -- Power Down MIN 4.5 TYP MAX 5.5 UNITS Volt
24 6 0.6
mA mA mA
8
MX93000
Absolute Maximum Ratings PARAMETER Supply Voltage Voltage on any I/O pin Current on any I/O pin Operating Ambient Temperature Storage Temperature 0 -65 Symbol VDD-GND MIN -0.3 GND-0.3 MAX 6.0 VDD+0.3 +-8 70 150 UNITS Volt Volt mA C C
NOTE: * These items are guaranteed by characterization, not production testing. 1.VDD=AVDD=5.0V, Temp=25C, Sampling Rate=8KHz, Linear Mode, fin=1 KHz, Measurement Bandwidth=300--3.4K Hz A/D Path=MIC --> PGA (0dB) --> A/D, No ALC. 2.VDD=AVDD=5.0V, Temp=25C, Sampling Rate=8KHz, Linear Mode, fin=1 KHz, Measurement Bandwidth=300--3.4K Hz D/A Path=D/A --> SPK (0dB) output 3.Vin=0dB -- -50dB, fin=1KHz. 4. Input is grounded. Measurement Bandwidth=300 -- 3.4K Hz. 5. A/D & D/A input grounded, Frequency=1KHz, 100m Vp signal on power supply. 6. 0 dB at A/D input, D/A input grounded, then D/A output measured. 7. 0 dB at D/A input, A/D input grounded, then A/D output measured. 8. Power supply current does not include output loading.
9
MX93000
SPECIAL CODEC TIMING DESCRIPTION :
TIMING Tfs Tfsh DESCRIPTION from Vmckh1 to Vfsh1 Holding time for Frame Sync. from Vfsh1 to Vfsh2 setting time for Codec Transmit Data from Vmckh1(n) to DX(n) data ready Holding time for Codec Receive Data from DR(n) data ready to Vmckh2(n) Holding time for Codec Receive Data from Vmckl(n) to DR(n) ending from Vfsh1 to Venl from Vfsh1 to Venh Setting time for uP/DSP Transmit SDATA from Vupenl to uP/DSP SDATA (n) ready (where Tupen1 + Tups1 must be less than FS) Setting time for uP/DSP Transmit SDATA from Vfsh1(n+1) to uP/DSP SDATA (n+1) ready Holding time for uP/DSP Transmit SDATA from Vfsh1(n+1) to uP/DSP SDATA(n) ending from Vfsh(n+1) to Codec read SDATA(n) from Vupenl to uP/DSP changing its SDATA interface into input port from Vfsh1 to Codec changing its SDATA interface into output port Setting time for Codec Transmit SDATA from Vcdi2o to Codec SDATA(n) ready Setting time for Codec Transmit SDATA from Vfsh1(n+2) to Codec SDATA(n+1) ready Holding time for Codec Transmit SDATA from SDATA(n) ready to Vfsh1(n+2) from Venh to Codec changing its SDATA interface into input port from Vfsh1(n+1) to uP/DSP reading SDATA(n) from Vfsh1 to uP/DSP changing its SDATA interface into output port 40 40 40 MIN 0 MCLK MAX UNIT ns ns
Tdxs
110
ns
Tdrh1
0
ns
Tdrh2
150
ns
Tupen1 Tupen2 Tups1
40 40 40
FS FS FS
ns ns ns
Tups2
40
FS
ns
Tuph
40
Tups2
ns
Tcdrd Tupo2i
20 FS
ns ns
Tcdi2o
20
ns
Tcds1
20
ns
Tcds2
20
ns
Tcdh
FS
ns
Tcdo2i
20
ns
Tuprd Tupi2o
FS FS
ns ns
10
MX93000
SPECIAL CODEC TIMING DIAGRAM :
PCM CODEC MASTER CLOCK , FRAME SYNC. & DATA TIMING
MCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FS
u-LAW,A-LOW DR/X
MSB
1
2
3
4
5
6
7
8
LSB
LINEAR DR/X
MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LSB
Vmckh1 MCLK
Vmckh2 Vmckl
Vmckh1
(n) 1
(n+1)
2
Tfs Tfsh Vfsh2 Vfsh1 Tdxs
Tdxs
FS
DX
1
(n)
2 (n+1)
Tdrh1
Tdrh2
DR
1 (n)
2 (n+1)
11
MX93000
PCM CODEC CONTROL REGISTER R/W TIMING
CODEC READ SDATA
n
n+1
n+2
FSR/X
1
2
Tupen1
3
4
5
6
7
8
9
10
11
12
13
14
Tupen2
SDEN\
Venl Tups1 Tuph Tuph Tups2 A0 D7 D6 D5 D4 D3 D2 D1 D0
Venh
uP/DSP SDATA INTERFACE
A2 n
A1 n+1 Tcdrd
CODEC SDATA INTERFACE
CODEC READ SDATA
CODEC WRITE SDATA
Vfsh1 n
n+1
n+2
FSR/X
1
2
Tupen1
3
4
5
6
7
8
9
10
11
12
13
14
Tupen2
SDEN\
Vcdi2o Tcdi2o Tcds1 Tcds2 Tcdh A1 n+1 Tuprd Tupi2o A0 D7 D6 D5 D4 D3 D2 D1 D0 Tcdo2i
CODEC SDATA INTERFACE
A2 n Tupo2i
uP/DSP SDATA INTERFACE
uP/DSP READ SDATA
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MX93000
REGISTERS DEFINITION :
REGISTER 0: ADDRESS BIT DATA A2 0 A1 0 A0 0
DATA BIT POWER-ON DESCRIPTION
D7 0
SWA-CTL
D6 0
D5 0
SWB-CTL
D4 0
D3 0
D2 0
D1 0
SWF-CTL
D0 0
SWG-CTL
SWC-CTL SWD-CTL SWE-CTL
(SWA-CTL)
D(7,6) = (1,1) : path of SWA is "c==>A" PGA setting following LINE-IN GAIN SETTING = (1,0) : path of SWA is "b==>A" PGA setting following AUX-IN GAIN SETTING (see Note 1.) = (0,1) : path of SWA is "a==>A" PGA setting following MIC-IN GAIN SETTING = (0,0) : path of SWA is "d==>A" (grounding to AG) D(5) = (1) = (0) = (1) = (0) = (1) = (0) = (1) = (0) = (1) = (0) = (1) = (0) : path of SWB is "CLOSE" : path of SWB is "OPEN" : path of SWC is "b==>A" : path of SWC is "a==>A" : path of SWD is "CLOSE" : path of SWD is "OPEN" : path of SWE is "CLOSE" : path of SWE is "OPEN" : path of SWF is "CLOSE" : path of SWF is "OPEN" : path of SWG (ATTENUATOR) is "A==>b" ATTENUATOR setting following ALARM-OUT SETTING : path of SWG (ATTENUATOR) is "A==>a" ATTENUATOR adjusted by external VR1
(SWB-CTL)
(SWC-CTL)
D(4)
(SWD-CTL)
D(3)
(SWE-CTL)
D(2)
(SWF-CTL)
D(1)
(SWG-CTL)
D(0)
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MX93000
REGISTER 1 : ADDRESS BIT DATA A2 0 A1 0 A0 1
DATA BIT POWER-ON DESCRIPTION
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
LINE-IN GAIN SETTING
LINE-OUT GAIN SETTING
(LINE-IN GAIN SETTING) D(7-4) = (F) - (0) : 22.5dB - 0dB, 1.5dB/STEP (LINE-OUT GAIN SETTING) D(3-0) = (F) - (0) : 22.5dB - 0dB, 1.5dB/STEP
REGISTER 2 : ADDRESS BIT DATA A2 0 A1 1 A0 0
DATA BIT POWER-ON DESCRIPTION
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
AUX-IN GAIN SETTING
MIC-IN GAIN SETTING
(AUX-IN GAIN SETTING) D(7-4) = (F) - (0) : 22.5dB - 0dB, 1.5dB/STEP (MIC-IN GAIN SETTING) D(3-0) = (F) - (0) : 22.5dB - 0dB, 1.5dB/STEP
14
MX93000
REGISTER 3 : ADDRESS BIT DATA A2 0 A1 1 A0 1
DATA BIT POWER-ON DESCRIPTION
D7 0
D6 0
D5 0
D4 0
D3 1
D2 1
D1 1
D0 1
SWH-CTL SWI-CTL SWJ-CTL SWK-CTL
ALARM-OUT ATTENUATOR SETTING
(SWH-CTL)
D(7)
= (1) = (0) = (1) = (0) = (1) = (0) = (1) = (0)
: path of SWH is "CLOSE" : path of SWH is "OPEN" (see Note 1.) : path of SWI is "CLOSE" : path of SWI is "OPEN" : path of SWJ is "CLOSE" : path of SWJ is "OPEN" : path of SWK is "CLOSE" : path of SWK is "OPEN" (see Note 1.)
(SWI-CTL)
D(6)
(SWJ-CTL)
D(5)
(SWK-CTL)
D(4)
(ALARM-OUT ATTENUATOR SETTING) D(3-0) = (F) - (0) : -45dB - 0dB 3dB/STEP where ALARM-OUT ATTENUATOR ==> ATTENUATOR CHANNEL-b SPK-OUT ATTENUATOR ==> ATTENUATOR CHANNEL-a (adjusted by VR1 10Ky)
15
MX93000
REGISTER 4 : ADDRESS BIT DATA DATA BIT POWER_ON DESCRIPTION (PDN) A2 1 D7 0 A1 0 D6 0 PDN A0 0 D5 0 ECHO D4 0 D3 0 D2 0 D1 0 D0 0
MASTER CLOCK
CODEC FORMAT
D(6)=1 : POWER DOWN MODE. a.When D(6) is set to 1, the MX93000 will enter power down mode after 5 MCLKS. The 5_MCLK period is for the initialization of digital circuits in the MX93000. b.When the MX93000 enters power down mode, it will clear all registers after 20us. c.When system power recovers and MCLK is enabled, the MX93000 will wake up after 30ms and then user can restore all registers.
up set PDN = 1
MCLK Keep Hi or Low CKTs power_on
MCLK (pin 6) PDN\ (pin12)
REG4 PDN bit CODEC power-consumption
> 5 MCLKs 20 us 30 ms
(ECHO)
D(5)
= (1):ECHO CANCELLER ON (3-6dB) (0):ECHO CANCELLER OFF
(MASTER CLOCK)
D(3,2) = (0,0): 1.536 MHz
(CODEC FORMAT)
D(1,0) = = = =
(1,1): (1,0): (0,1): (0,0):
LINEAR CODER & DECODER (16 BITS FORMAT) LINEAR CODER & DECODER (16 BITS FORMAT) A-LAW CODER & DECODER (8 BITS FORMAT) u-LAW CODER & DECODER (8 BITS FORMAT)
LINEAER 16 BITS FORMAT : 14 BITS RESOLUTION with 2LSB=0 SIGN\SCALE POSITIVE NEGATIVE MIN 0000 0000 0000 0000 1111 1111 1111 1100 MAX 0111 1111 1111 1100 1000 0000 0000 0000
16
MX93000
REGISTER 5 : ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION (ALC) D(1) = 1 : ALC loop gain attenuate 6dB D(1) = 0 : ALC loop gain attenuate 0dB @@ reserve for internal use REGISTER 6 : ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION @@ reserve for future use REGISTER 7 : ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION (READ) D(3) = 1 : read data from register 0-6 = 0 : write data to register 0-7 (REGISTER ADDRESS) D(2-0) : 1.When READ = 1, READ will be cleared automatically. 2.When READ = 1, next uP/DSP SDEN\ signal active low, CODEC will change CODEC SDATA interface into output and following the last time REGISTER ADDRESS to output the content of register. Note 1. :When using SWK or SWH, the path between AUX and SWA will disconnect. Oppositely, if using the path between AUX and SWA, then SWK and SWH will be invalid. A2 1 D7 0 A1 1 D6 0 A0 1 D5 0 D4 0 D3 0 READ D2 0 D1 0 D0 0 A2 1 D7 0 A1 1 D6 0 A0 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 A2 1 D7 0 A1 0 D6 0 A0 1 D5 0 D4 0 D3 0 D2 0 D1 0
ALC
D0 0
REGISTER ADDRESS
17
MX93000
THE FOLLOWING LIST IS BASIC COMPONENT REQUIRED :
REFERANCE R1 R2 R3 R4,R5 PART 620 y 2 Ky 75 Ky DESCRIPTION matching resistor; to reflect 600y at the transformer primary current-limit resistor; to limit MIC bias current ; please follow MIC specification time constant ; ALC release time constant = R3 * C6 to scale down SYSTEM power supply (VPOW) and compare with 1.25V to do power-down check to scale down BATTERY (VBAT) and compare with 1.25V to do power-down check 10Ky 10 Ky 330 Ky 200 Ky 0.1 uF 10 uF 10 uF 47 uF 1uF 1000 pF 0.1 uF 0.1 uF 10 uF 10Ky the time constant for power-on-reset circuits ; where RC=R8 * C11 current-limit resistor for Q1 discharge path for ALC circuit when Q1 turns off to attenuate line-in signal DC blocking capacitor to decouple analog virtual ground ; where AG = VREF = 2.25v DC blocking capacitor time constant ; ALC Attack time contant > 2ky 10% * C6 DC offset cancellation decouple capacitor anti-aliasing capacitor decoupling capacitor for power supply of Codec digital circuit decoupling capacitor for power supply of Codec analog circuit the time constant for power-on-reset circuits ; where RC = R8 * C11 to attenuate the input signal from SWH or SWF ; if using digital volume control, connecting pin-27 VR to VREF ALC feedback component ; all NPN ( > 100) transistor can play this role to protect reset circuits from spike
R6,R7
R8 R9 R10 R11 C1,C4 C2,C3 C5 C6 C7 C8 C9 C10 C11 VR1 then Q1 D1
2N3904 1N4148
18
MX93000
PIN DESCRIPTIONS :
SYMBOL SDATA
PIN TYPE I/O(D)
PIN NUMBER 1
DESCRIPTION Bidirectional serial port ; It's an interface for microprocessor serial data transfer Serial data enable ; active low ; for starting to receive/transmit serial data (A2-D0) Transmit data pin (Codec serial data) Receive data pin (Codec serial data) Codec frame sync ; 8KHz frame synchronization clock for the transmit/receive channel Master clock input (MCLK=1.536 MHz) When this pin is continuously high or low and set register4/bit6 "PDN=1", then the MX93000 will enter power-down mode Digital power ; 5V power supply for all internal digital logic Digital ground ; ground reference (0V) for all internal digital logic Power on reset (active high) ; Determined by PDN\ and BATT\ input signal Battery detector output (active low); referenced to 1.25V Battery detector input ; the voltage is divided from battery power for reference to 1.25V Power down detector output (active low) ; referenced to 1.25V Power down detector input ; System DC power is divided and then connected so as to compare with reference voltage (1.25v) Telephone signal line input , can be switched to PGA. Telephone line output (postive) with PGA ; where PGA gain is from 0 to 22.5dB Telephone line output (negative) with PGA ; where PGA gain is from 0 to 22.5dB
SDEN\
I (D)
2
DX DR FS
O (D) I (D) I (D)
3 4 5
MCLK
I (D)
6
VDD GND
(D) (D)
7 8
PRST
O (D)
9
BAT\ VBAT
O (A) I (A)
10 11
PDN\ VPOW
O (A) I (A)
12 13
LIN LOUT1
I (A) O (A)
14 15
LOUT2
O (A)
16
Note : "D" means digital "A" means analog
19
MX93000
SYMBOL AVDD AGND
PIN TYPE (A) (A)
PIN NUMBER 17 18
DESCRIPTION Analog power supply ; 5V power for all internal analog circuitry Analog ground ; ground reference(0V) for all internal analog circuitry Internal analog ground ; nominal 2.25V and must not be used to sink or source current Microphone signal input, can be switched to PGA, where PGA gain is from 0 to 22.5dB 1.Auxiliary signal input, can be switched to PGA, where PGA gain is from 0 to 22.5dB 2.As an output port for Aout or an input port for attenuator or line driver Programmable Gain Amplifier output port Auto level control time constant ; where RC=2K10%*C6 Offset cancellation capacitor (positive) ; normally add a 1 uF capacitor 1.Anti-aliasing filter; normally add a 1000pF capacitor 2.As an input port for Codec or an output port for SWD or SWI Voltage reference ; normal 2.25V and can sink 500uA Speaker volume control ; use a variable resistor 10ky Speaker output ; it can be attenuated by VR or control register from 0 to -45dB
AG
O (A)
19
MIC
I (A)
20
AUX
I/O (A)
21
PGAC ALCRC ALCC
O (A) O (A) O (A)
22 23 24
FILT
I/O (A)
25
VREF VR SPK
O (A) 0 (A) O (A)
26 27 28
20
MX93000
APPENDIX :
MX93000 Buglist
1.A/D Full Swing : Full Swing of A/D is 3.4 Volt in stead of the original target 3.0 Volt. 2.Maximum External Attenuation of SPK through VR pin is only 27 dB. 3.Line Drive Gain: Line driver will behave as a gain loss rather than a gain loss rather than a gain stage whenever line driver inputs are come from SWK and/or SWJ. Line Driver gain if input from SWE 0.0 dB 1.5 dB 3.0 dB 4.5 dB 6.0 dB 7.5 dB 9.0 dB 10.5 dB 12.0 13.5 15.0 16.5 18.0 19.5 21.0 22.5 dB dB dB dB dB dB dB dB SWK/SWJ -9.0 dB -8.7 dB -7.6 dB -6.8 dB -6.0 dB -5.3 dB -4.6 dB -4.0 dB -3.5 -3.0 -2.6 -2.2 -1.9 -1.6 -1.4 -1.2 dB dB dB dB dB dB dB dB
4.The larger of VREF's bypass capacitor, the better of D/A idle channel noise. 100 uF rather than 10uF can get a good performance.
21
MX93000
28-PIN PLASTIC SOP (300 mil)
ITEM A B C D E F G H I J K L
NOTE:
MILLIMETERS 17.83 max. 1.194 max. 1.27 [TP] .41 [Typ.] .20 min. 2.54 max. 2.34 .13 10.31 .31 7.60 .13 1.37 .20 .25 [Typ.] .91 .20
INCHES .702 max. .026 max. .047 [TP] .016 [Typ.] .008 min. .100 max. .092 .005 .406 .012 .299 .005 .054 .008 .010 [Typ.] .036 .008
28
15
1 A
14
H I G F K J
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at a maximum material condition.
D
C
B
E L
28-PIN PLASTIC DIP (300 mil)
ITEM A B C D E F G H I J K L M
NOTE:
MILLIMETERS 34.29 max .64 [REF] 2.54 [TP] .46 [Typ.] 32.99 1.52 [Typ.] 3.30 .25 .51 [REF] 3.30 2.5 3.81 max. 7.87 2.5 7.32 2.5 .25 [Typ.]
INCHES 1.350 max .025 [REF] .100 [TP] .018 [Typ.] 1.300 .060 [Typ.] .130 .010 .020 [REF] .130.098 .150 max. .310.098 .288.098 .010 [Typ.]
F D E C B M 2~8 H G I J 1 A 14 K L 28 15
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at a maximum material condition.
22
MX93000
ORDERING INFORMATION
MX
MXIC COMPONY PREFIX
93
000
K
C
COMMERICIAL 0 ~ 70x C
FAMILY PREFIX
PACKAGE TYPE K:PDIP S:SOP
PRODUCT NUMBER
23
MX93000
MACRONIX INTERNATIONAL CO., LTD
HEADQUARTERS :
TEL : +886-3-578-8888 FAX : +886-3-578-8887
EUROPE OFFICE :
TEL : +32-2-456-8020 FAX : +32-2-456-8021
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TEL : +81-44-246-9100 FAX : +81-44-246-9105
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TEL : +65-747-2309 FAX : +65-748-4090
TAIPEI OFFICE :
TEL : +886-2-2509-3300 FAX : +886-2-2509-2200
MACRONIX AMERICA INC.
TEL : +1-408-453-8088 FAX : +1-408-453-8488
CHICAGO OFFICE :
TEL : +1-847-963-1900 FAX : +1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
24

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